The present invention relates to semiconductor devices, the fabrication process thereof, and application thereof. Particularly, the present invention relates to a semiconductor device having a transistor of LDMOS structure, the fabrication process thereof, and application thereof.
In this specification, an LDMOS transistor (lateral double diffuse insulation gate field transistor) is defined as a field effect transistor having a low impurity concentration layer formed so as to surround the source region with a conductivity type opposite to the conductivity type of the source or drain region. The LDMOS transistor thereby uses a surface part of the low impurity concentration layer right underneath the gate electrode as a channel region. Further, “conventional MOS transistor” used in this specification is defined as a MOS transistor having the structure in which a drain region is formed with an impurity concentration level higher than in a channel region.
In the field of the semiconductor devices that include a circuit such as regulator or DC/DC converter, there is a demand for a semiconductor device of high output current in these days in view of the need of using the semiconductor device in wide variety of applications. An LDMOS transistor is characterized by low ON-resistance and thus draws attention because of its capability of increasing the output current. An LDMOS transistor has a unique feature, originating from its structure, in that miniaturization is possible while maintaining high breakdown voltage and it becomes possible to reduce the chip area with the use of such an LDMOS transistor.
An LDMOS transistor is a field effect transistor in which a low impurity concentration layer (channel well) is formed so as to surround a source region with a conductivity type opposite to the conductivity type of source and drain regions. A channel is formed at a surface of the low impurity concentration layer right underneath the gate electrode.
FIG. 1A shows an example of an n-channel LDMOS transistor.
Referring to FIG. 1A, a polysilicon gate electrode 106 is formed over a silicon substrate 102 of n-type having a high resistivity via a gate oxide film (gate insulation film) 104, wherein there is formed a channel well 108 in the silicon substrate 102 by introducing and activating a p-type impurity element while using an edge of the gate electrode 106 at the side of the source region as a mask. Thereby, a part of the channel well 108 thus formed serves for the channel region. Further, a source region 110 of n-type and a drain region 112 of n-type are formed in the silicon substrate 102 with low resistance by an ion implantation process of an n-type impurity element conducted while using the gate electrode 106 as a mask and subsequent thermal activation. Further, there is provided an interlayer insulation film 114 and electrodes 116 and 118 are formed respectively in connection with the n-type source region 110 and the n-type drain region 112. Reference should be made to Patent Reference 1.
In the case of using an LDMOS transistor for a high voltage transistor, it is generally practiced, in order to relax the electric field caused between the drain electrode and the gate electrode, to increase the thickness of a gate oxide film 104a as shown in FIG. 1B or by interposing a thick field oxide film 104b as shown in FIG. 1C. Reference should be made to Patent Reference 2, for example. Here, it should be noted that the reference numeral 120 represents a drain region of medium concentration level of n-type formed underneath the thick oxide film 104a or 104b with an impurity concentration level higher than the n-type silicon substrate 102 but lower than the n-type drain region 112.
With the structure in which the thickness of the gate oxide film is not increased at the drain edge part as in the case of FIG. 1A, the n-type drain region 112 is located right underneath the gate electrode and the breakdown characteristic is tend to be deteriorated because of the concentration of electric field in such a part.
Thus, in order to improve the breakdown voltage of an LDMOS transistor, there is proposed a method of disposing the high concentration drain region with a separation from the gate electrode.
FIG. 2 is a cross-sectional diagram showing a conventional n-channel LDMOS transistor.
Referring to FIG. 2, there is formed a drain well 21 of n-type in a p-type semiconductor substrate (p-type substrate) 1, wherein there is formed a p-type channel well 23 in the n-type drain well 21, and there is further formed an n-type source region 11s in the p-type channel well 23. Inside the n-type drain well 21, there is formed a drain region lid of n-type with a separation from the p-type channel well 23 with a concentration level higher than the n-type drain well 21. Further, there is formed an n-type gate electrode 11g of polysilicon over and across the n-type drain well 21 for the part between the n-type source region 11s and n-type drain region 11d and further the p-type channel well 23 but with a separation from the n-type drain region 11d. The gate electrode 11g is provided via a gate oxide film 11ox. With this structure, the surface of the p-type channel well 23 right underneath the n-type gate electrode 11g becomes the channel region.
With the n-channel LDMOS of such a structure, the On-resistance is determined as a sum of the channel resistance, the drain resistance and the source resistance. Thus, with the present construction, the source resistance is eliminated by forming the n-type source region 11s in self-alignment with the n-type gate electrode 11g. 
However, with the structure of FIG. 2, there appears a high drain resistance associated with the resistance component of the n-type drain well 21, while there is caused a decrease of channel resistance when a high electric field is induced in the channel region with application of the gate voltage. Under such a situation, the drain resistance occupies the majority part of the transistor resistance, and there is caused a problem in that it is not possible to increase the drain current.
Further, there has been a problem with the construction of FIG. 2 in that, because the drain region is easily destroyed when a parasitic bipolar transistor has caused conduction as a result of the high electric field caused in the MOS transistor by the drain voltage. When this occurs, it is not possible to obtain a normal operational waveform.
In order to improve the foregoing problem, there is proposed a method of forming the drain region and the source region in the form of double diffusion structure in the LDMOS transistor as proposed in Patent Reference 1.
Further, there is proposed a method of conducting an impurity injection to the surface part of the well located between the gate electrode and the high-concentration drain region in a self-alignment manner for lowering the resistance thereof and for improving the drain breakdown voltage of LDMOS transistor. Reference should be made to Patent Reference 3. However, the LDMOS transistor disclosed in Patent Reference 3 lacks the feature of self-alignment at the source side, and thus, there arises a problem in that the source resistance is not eliminated completely. Thus, the construction of this prior art reference is not suitable for achieving low ON-resistance.
In view of the foregoing problems of the prior art, the inventor of the present invention has attempted formation of both the source side and the drain side by a self-alignment process. FIG. 3 shows the LDMOS transistor used in this related art.
FIG. 3 is a cross-sectional diagram showing the n-channel MOS transistor of this related art, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to FIG. 3, the LDMOS transistor of the related art is constructed on a p-type substrate and includes therein an n-type source region 11s, an n-type drain region 11d, an n-type gate oxide 11ox, an n-type gate electrode 11g, and an n-type drain well 21, wherein a p-type channel well 23 is formed inside the n-type drain well 21. Thereby, it should be noted that the n-type source region 11s is formed in a self-aligned process with regard to the n-type gate electrode 11g. Further, an n-type drain region 4 of intermediate concentration level is formed on the surface part of the n-type drain well 21 at the side of the n-type drain region lid with regard to the n0type gate electrode 11g. It should be noted that the drain region 24N of the intermediate concentration level is formed in a self-alignment process with regard to the n-type gate electrode 11g. The drain region 24 of the intermediate concentration level is formed shallower than the n-type drain region 11d. 
Further, there is disclosed a construction in which the drain region 24 of the intermediate concentration and the gate electrode 11g are partially overlapped in the structure of FIG. 16 Reference should be made to Patent Reference 4, for example.